The present invention relates to a semiconductor memory, particularly a ferroelectric memory, and write and read methods of the same.
A semiconductor memory, particularly a ferroelectric memory, related to the present invention includes cells each having an arrangement as shown in FIG. 21. That is, each cell has one transistor Tr and one capacitor C. One terminal of the capacitor C is connected to one of the source and drain diffusion layers of the transistor Tr. The other terminal of the capacitor C is connected to a plate line PL. The gate of the transistor Tr is connected to a word line WL. The other of the source and drain diffusion layers is connected to a bit line BL.
A write operation to the cell having this arrangement will be described below with reference to FIG. 22. In FIG. 22, arrows indicate the directions of polarization P. For example, an upward arrow ".Arrow-up bold." indicates that the capacitor polarization direction is from an electrode connected to the plate line PL to an electrode connected to the transistor Tr. Conversely, a downward arrow ".dwnarw." indicates that the capacitor polarization direction is from the electrode connected to the transistor Tr to the electrode connected to the plate line PL.
As shown in FIG. 22, the write operation is performed in three steps (a), (b), and (c). In step (a), a ground voltage Vss or a power supply voltage Vcc is applied in accordance with data to be written in the bit line BL. That is, the ground voltage Vss is applied when "0" data is to be written, and the power supply voltage is applied when "1" data is to be written. Letting Vth be the threshold voltage of the transistor Tr, Vcc+Vth is applied to the word line WL, and the ground voltage Vss is applied to the plate line PL. In this step, when "0" data is to be written, the polarization of the capacitor C remains unchanged. When "1" data is to be written, downward polarization is stored in the capacitor C.
In step (b), the potentials of the bit line BL and the word line WL are not changed from those in step (a), and only the plate line PL is changed to the power supply voltage Vcc. Consequently, upward polarization is stored in the capacitor C when "0" data is to be written, and the polarization of the capacitor C remains unchanged when "1" data is to be written.
In final step (c), the plate line PL is returned to the ground voltage Vcc. In this step, the polarization of the ferroelectric capacitor C remains the same.
In the above three steps, upward or downward polarization is stored in the ferroelectric capacitor C in accordance with the potential applied to the bit line BL. Next, an operation of reading out written data will be described below with reference to FIG. 23 showing the read procedure and a timing chart of FIG. 24 showing potential changes on the individual control lines.
Step (a) corresponds to a precharge cycle in which the bit line BL is grounded. At this stage, a sense amplifier (not shown) for reading the potential of the bit line BL is kept disconnected from the bit line BL. Both the word line WL and the plate line PL are grounded. In this step, the polarization direction stored in the capacitor C remains unchanged.
In step (b), the power supply voltage Vcc is applied to the word line WL and the plate line PL. If "0" data, i.e., upward polarization is stored in the ferroelectric capacitor C, the polarization direction in the capacitor C does not change. Accordingly, the potential of the bit line BL also remains unchanged from the ground voltage Vss. However, if "1" data, i.e., downward polarization is stored in the ferroelectric capacitor C, the polarization direction in the capacitor C changes from downward to upward. In accordance with this polarization inversion, electric charge from the ferroelectric capacitor C moves to the bit line BL. Consequently, the potential of the bit line BL rises from the ground voltage Vss to, e.g., about 0.7 V.
In step (c), the potential of the plate line PL is returned to the ground voltage Vss. In this step, no polarization change occurs in the ferroelectric capacitor C. In step (b), however, the potential of the bit line BL remains at the ground voltage Vss when "0" data is written, and has risen to about 0.7 V when "1" data is written. This potential difference is finally amplified and read out by a sense amplifier (not shown). Since this read operation destroys the stored data in the ferroelectric capacitor C, the write operation must be again performed subsequently to the read operation.
FIG. 25 shows the circuit configuration of a ferroelectric memory related to the present invention. This ferroelectric memory includes a cell array 121 in which cells each having the aforementioned arrangement are arranged in a matrix, a word line driver 123 for driving the word line WL, a plate line driver 125 for driving the plate line PL, a sense amplifier and a bit line driver 124 for driving the bit line BL and amplifying and reading out the potential of this bit line BL, and a controller 122 for controlling the word line driver 123, the plate line driver 125, the sense amplifier, and the bit line driver 124.
This ferroelectric memory, however, requires the three control lines, i.e., the bit line BL, the word line WL, and the plate line PL, to drive the cells, and design of timings for driving at different timings is cumbersome. Additionally, driving the potentials of these control lines requires the word line driver 123, the plate line driver 125, the sense amplifier, the bit line driver 124, and the controller 122 for controlling these components. This complicates the circuit configuration and leads to an increase in the chip size.